1. Field of the Invention
The present invention relates to an insulated gate semiconductor device such as a MIS transistor, and particularly, to a semiconductor device capable of reducing drain capacitance and grounding inductance, to realize high power gains at high frequencies.
2. Description of the Prior Art
FIGS. 18 and 19 are sectional views showing conventional MOSFETs. The MOSFET of FIG. 18 employs a p silicon wafer 1 including an n+ drain region 4 and an n+ source region 5. A thin gate oxide film 2 of 50 to 100 nanometers thick is formed on the wafer 1, and a gate electrode 3 is formed on the gate oxide film 2. An insulation film 6 made of, for example, PSG covers the gate electrode 3. The wafer 1 is composed of a p+ semiconductor substrate 1a and a p semiconductor layer 1b epitaxially grown on the substrate 1a. The gate electrode 3 is made of polycrystalline silicon, refractory metal, or silicide of the refractory metal. A p+ diffusion region 10 extends from the top surface of the layer 1b to the substrate 1a. The diffusion region 10 is electrically connected to a source electrode 8, to ground the source to the substrate 1a.
The MOSFET of FIG. 19 employs an SOI (Silicon on Insulator) structure. A gate oxide film 2 is formed on a silicon wafer 1 between an n+ drain region 4 and an n+ source region 5. A gate electrode 3 is formed on the gate oxide film 2. The SOI structure is usually composed of an insulator and silicon disposed on the insulator. The structure of FIG. 19 interposes an oxide film 9 between silicon layers. The oxide film 9 is in contact with the bottoms of the drain and source regions 4 and 5. The oxide film 9 is entirely formed through the wafer 1. The drain region 4 extends in a p semiconductor layer of the wafer 1 and is electrically connected to a drain wiring electrode 7. The source region 5 extends in the same p semiconductor layer of the wafer i and is electrically connected to a source wiring electrode 8. The electrode 8 has a bonding area for a grounding wire 11 for grounding the source.
MOSFETs are frequently used for high-frequency circuits. One of the important factors of such MOSFETs is power gains at high frequencies. The larger the power gains the better. To increase the power gains, the MOSFETs must increase their transconductance gm while reducing inductance such as grounding inductance, capacitance such as drain capacitance, and floating impedance. FIG. 20 shows a typical equivalent circuit of a high-frequency MOSFET. In the MOSFET of FIG. 18, drain-substrate capacitance, or drain-source capacitance Cds is dependent on a contact area between the drain region 4 and the layer 1b. To drop the drain-substrate capacitance Cds, the prior art reduces the drain area. This prior art, however, is limited by processing techniques and accuracy.
In the MOSFET of SOI structure of FIG. 19, the oxide film 9 is entirely formed through the wafer 1. This may reduce the drain-substrate capacitance Cds but deteriorate heat dissipation radiation. Accordingly, the prior art must provide higher thermal resistance, to deteriorate output power. Unlike the prior art of FIG. 18, the prior art of FIG. 19 is incapable of grounding the source through the bottom surface of the wafer, and therefore, it must bond the grounding wire 11 to the source. This may add a grounding inductance Ls of about 2 nH to the source.